1. Field of the Invention
The present invention relates to a control circuit for controlling a driving circuit which provides signals to a displaying means such as a liquid crystal display for processing numerous digital data at high-speed. More particularly, the present invention relates to a control circuit in which there have been considered to cope with noise and undesired electromagnetic radiation in the control circuit.
2. Discussion of the Background
A conventional control circuit for controlling a driving circuit which provides signals to a displaying means such as a liquid crystal display for processing digital data at high speed generates undesired electromagnetic radiation when a digital signal is switched whereby other appliances are badly affected. Conventionally, there have been considered such as reinforcing of GND (i.e., lowering of grounding resistance), balancing of the circuit, providing the controlling circuit with a filter or shielding the controlling circuit with a metallic enclosure. Balancing of the circuit as mentioned herein indicates that wiring are designed so as not to cross with each other or the GND which functions as a returning path is reinforced in underlying layers of high-speed cables.
Accompanying progresses in digital electronics technology, high-speed processing of data is improving, and the switching speed of digital signals is accordingly increasing, whereby electric changes are transformed into electromagnetic energy so as to be radiated at the time of switching as electromagnetic waves and badly affect peripheral electric appliances. While consideration has been conventionally taken in view of the controlling circuit itself such as reinforcing GND, providing the controlling circuit with a filter or designing of wiring, consideration related to a timing controller of the liquid crystal display which serves as a generating source is still not sufficient.
As a consideration for coping with noise and undesired radiation of digital signals in a propagation path, a capacitor or a filter which is comprised of inductors may be provided on a wiring board. However, it may happen that the delay of signals owing to the filter becomes large at certain filter constants, and no set up time and hold time can be secured. Thus, a drawback is presented in that there are restrictions in the selection of filters.
Techniques for decreasing such undesired electromagnetic radiation are disclosed in Japanese Unexamined Patent Publication No. 232317/1991, Japanese Unexamined Patent Publication No. 219016/1992, Japanese Unexamined Patent Publication No. 186480/1996 and Japanese Unexamined Patent Publication No. 171531/1985.
In Japanese Unexamined Patent Publication No. 232317/1991 there is disclosed a technique in which a delay circuit for shifting phases of signals input to each output buffer is provided for the sake of decreasing the number of output buffer that simultaneously activate. However, it is in danger that the number of gates may increase accompanying the provision of a delay in each signal. In Japanese Unexamined Patent Publication No. 219016/1992, there is disclosed a technique in which varying timings of output data are respectively shifted by applying phase differences to clock pulses which are respectively input to a plurality of flip-flops. However, the interval for shifting the output timings can not be selected, and it may be that the noise level may increase up to a prescrived signal frequencies at which they synchronize or interfere with the phase shifting amount, while setting of one phase difference can not result in low noises and low EMIs when the frequency has been changed. Further, in Japanese Unexamined Patent Publication No. 186480/1996, there is disclosed a technique in which a multi-layered clock generating circuit is provided and each output buffer is activated by several types of clock signals which are of same frequency and which phases are uniformly shifted. However, when employing a multi-layered clock generating circuit, electromagnetic waves may be radiated by the multi-layered clock generating circuit itself, and the number of gates comprising the multi-layered clock generating circuit itself increases. In Japanese Unexamined Patent Publication No. 171531/1985, there is disclosed a technique in which there is provided at the side of the driving circuit a means for shifting phases of each video signal. However, in case the intervals of outputted timings for shifting phase are kept constant and the signal is a signal such as a picture image signal which keeps on changing, it may happen that generated noise synchronizes and increases at certain frequencies due to the shifting of the data signals and phase differences as discussed above.
It is an object of the present invention to solve such problems and to provide a control circuit for decreasing radiation of electromagnetic waves and, decreasing noise accompanying the high-speed processing of data.